1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Background Art
With a growing trend in recent years toward large-scale integration and miniaturization of semiconductor devices, it is becoming extremely important to reduce an isolation width between elements constituting a semiconductor device.
FIG. 28 is a sectional view showing a CMOS structure of a conventional semiconductor device. A semiconductor substrate 1 has an element isolation oxide film 3 formed in a predetermined region thereof. P wells 4 and N wells 5 are further formed in the semiconductor substrate 1. A PMOSFET formed on an N well 5 has a P type diffusion layer 6, and an NMOSFET formed on a P well 4 has an N type diffusion layer 7. Illustration of gate electrodes and the like of the PMOSFET and the NMOSFET is omitted here. The element isolation oxide film 3 electrically isolates P type diffusion layers 6 formed on N wells 5 from each other, and N type diffusion layers 7 formed on P wells 4 from each other, respectively. The element isolation oxide film 3 also electrically isolates a P well 4 from a P type diffusion layer 6 formed on an N well 5, and an N well 5 from an N type diffusion layer 7 formed on a P well 4, respectively.
Now in reference to FIGS. 29 through 34, an example of steps of manufacturing the CMOS structure of the semiconductor device shown in FIG. 28 will be described. First, an oxide film 8 is formed in a thickness of 10-30 nm on a main surface of the semiconductor substrate 1, and a nitride film 9 is deposited thereon by 100-200 nm. Thereafter, a photoresist (not shown) is formed and patterned so that an opening is provided in a region in which the element isolation oxide film 3 is to be formed, and the photoresist is used as a mask to perform anisotropic etching, thereby forming an element isolation groove 2 having a depth of 200-400 nm in the region in which the element isolation oxide film 3 is to be formed (FIG. 29). An oxide film to be the element isolation oxide film 3 is deposited thereon by 300-600 nm to fill in the element isolation groove 2 (FIG. 30). Next, the element isolation oxide film 3 is planarized by means of CMP, dry etching, wet etching, or combination of these methods, while removing the element isolation oxide film 3 on the nitride film 9 (FIG. 31). The nitride film 9 is finally removed, and the step of forming the element isolation oxide film 3 is completed (FIG. 32).
Next, a photoresist 10a is formed in a thickness of 1-3 xcexcm and patterned so that an opening is provided in a region in which a P well 4 is to be formed. Then, boron which is a P type impurity ion is implanted at an acceleration voltage of 60 keV to 180 keV and at a dose of 2xc3x971012 to 2xc3x971013/cm2, thereby forming a channel cut layer 11 for preventing punch-through between elements. Thereafter, boron is further implanted at an acceleration voltage of 200 keV to 1 MeV and at a dose of 4xc3x971012 to 4xc3x971013/cm2, thereby forming a retrograde well 12 (FIG. 33). The impurity ion implantation is performed with an inclination (incident angle) of about 7 degrees for avoiding channeling. Further, doping is carried out for adjusting a threshold voltage at the NMOSFET, thereby forming the P well 4.
Subsequently, a resist 10b is formed in a thickness of 1-3 xcexcm and patterned so that an opening is provided in a region in which an N well 5 is to be formed. Then, phosphor which is an N type impurity ion is implanted at an acceleration voltage of 120 keV to 380 keV and at a dose of 2xc3x971012 to 2xc3x971013/cm2, thereby forming a channel cut layer 13 for preventing punch-through between elements. Thereafter, phosphor is implanted at an acceleration voltage of 400 keV to 2 MeV and at a dose of 4xc3x971012 to 4xc3x971013/cm2, thereby forming a retrograde well 14 (FIG. 34). The implantation of phosphor is also performed with an inclination (incident angle) of about 7 degrees for avoiding channeling. Further, doping is carried out for adjusting a threshold voltage at the PMOSFET, thereby forming the N well 5.
Although illustration is omitted, a gate electrode, a P type diffusion layers 6 and an N type diffusion layers 7 are thereafter formed, and an interlayer insulating film, a contact hole and a wiring layer are further formed, thereby completing an LSI device.
As shown in FIG. 33, the impurity ion implantation to form the P well 4 is performed with an inclination of about 7 degrees. In this case, due to the shadowing effect caused by the height of the resist and the presence of an impurity ion flowing in below the resist 10a, impurity ion distributions to be formed actually (i.e., the channel cut layer 11 and the retrograde well 12) are shifted with respect to a position of an opening of the resist mask 10a. That is, the position of the P well 4 is shifted.
Further, as shown in FIG. 34, the impurity ion implantation to form the N well 5 is also performed with an inclination similarly to that for forming the P well 4, so that impurity ion distributions to be formed actually (i.e., the channel cut layer 13 and the retrograde well 14) are also shifted in the same direction as the P well 4. That is, the position of the N well 5 is also shifted in the same direction as the P well 4.
Therefore, according to the above-described method of manufacturing the conventional semiconductor device, the boundary between a P well 4 and an N well 5 is shifted with respect to the position of the opening of the resist mask 10a or 10b, i.e., a designed position. As a result, the distance between the N well 5 and the N type diffusion layer 7 in the P well 4 increases at a mask boundary A at the impurity ion implantation to form the wells, resulting in an increase in an isolation width (effective isolation width) which is actually effective therebetween, however, the distance between the P well 4 and the P type diffusion layer 6 in the N well 5 is reduced, which results in a reduction of an effective isolation width therebetween. On the other hand, the distance between the P well 4 and the P type diffusion layer 6 in the N well 5 increases at a mask boundary B, so that an effective isolation width therebetween increases, which, however, results in a reduction of an effective isolation width between the N well 5 and the N type diffusion layer 7 in the P well 4. That is, the effective isolation widths between the wells and the diffusion layers become unbalanced.
FIG. 36 shows design values dn0 and dp0 indicating isolation widths between the N well 5 and the N type diffusion layer 7 in the P well 4 at the mask boundaries A and B, respectively. The values dn+ and dnxe2x88x92 indicate effective isolation widths between the N well 5 and the N type diffusion layer 7 in the P well 4 at the mask boundaries A and B, respectively. The values dpxe2x88x92 and dp+ indicate effective isolation widths between the P well 4 and the N type diffusion layer 6 in the N well 5 at the mask boundaries A and B, respectively.
FIG. 37 is a plan view for explaining the aforementioned problem of the well shift. In the drawing, P+ represents the P type diffusion layer and N+ represents the N type diffusion layer. The left direction of the drawing is defined as a 0 degree direction. For instance, when the impurity ion implantation to form the N well is performed at an incident angle of about 7 degrees from the 0 degree direction using a resist having an opening in a position for the N well indicated by solid lines as a mask, the N well is formed with a shift from the position of the opening of the resist, i.e., the designed position, as indicated by dotted lines in FIG. 37. Further, by performing the impurity ion implantation to form the P well at an incident angle of about 7 degrees from the 0 degree direction, the P well is also formed with a shift from the designed position as indicated by the same dotted lines.
As a result, the effective isolation width between the P well and the P type diffusion layer in the N well at a boundary C shown in FIG. 37 and that between the N well and the N type diffusion layer in the P well at a boundary D both become smaller than designed values.
Alternatively, the N well and the P well shall be formed, for example, by the impurity ion implantation from the 0 degree direction in an arrangement of the N well, the P well and the N type diffusion layer such as that shown in FIG. 38. At this time, the N well and the P well are shifted in a 180 degree direction from the designed position, which increases the effective isolation width between the N well and the N type diffusion layer positioned in the 0 degree direction with respect to the N well, resulting in an improved breakdown voltage performance therebetween. On the other hand, the effective isolation width between the N well and the N type diffusion layer positioned in the 180 degree direction with respect to the N well is reduced, resulting in a reduction in a breakdown voltage performance therebetween. The effective isolation widths between the N well and the N type diffusion layer positioned in 90 degree direction and 270 degree direction with respect to the N well remain at designed values, respectively. The relationship between the direction (angle) in which the N type diffusion layer is positioned with respect to the N well and the breakdown voltage therebetween in this case is plotted by solid line in a graph shown in FIG. 40.
Still alternatively, the N well and the P well shall be formed, for example, by the impurity ion implantation from the 0 degree direction in an arrangement of the N well, the P well and the P type diffusion layer such as that shown in FIG. 39. At this time, the N well and the P well are also shifted in the 180 degree direction from the designed position, which reduces the effective isolation width between the P well and the P type diffusion layer positioned in the 0 degree direction in the N well, resulting in a reduction in a breakdown voltage performance therebetween. On the other hand, the effective isolation width between the P well and the P type diffusion layer positioned in the 180 degree direction in the N well is increased, resulting in an improved breakdown voltage performance therebetween. The effective isolation widths between the P well and the P type diffusion layer positioned in the 90 degree direction and the 270 degree direction in the N well remain at designed values, respectively. The relationship between the direction (angle) in which the P type diffusion layer is positioned in the N well and the breakdown voltage therebetween in this case is plotted by dotted line in the graph shown in FIG. 40.
More specifically, as seen from the graph shown in FIG. 40, the breakdown voltage characteristics, i.e., the isolation characteristics between the P well and the P type diffusion layer and between the N well and the N-well diffusion layer vary, depending on the relationship between the direction of the impurity ion implantation when forming the wells and the direction in which the diffusion layers are positioned with respect to the wells. This means that limiting the positional relationship between the wells and the diffusion layers only in such a manner that the isolation characteristics are most improved enables the most effective arrangement of the wells and the diffusion layers. However, it is virtually impossible to limit the direction of the diffusion layers with respect to the wells to a single direction, so that the minimum value of the isolation width, i.e., the minimum isolation width between the wells and the diffusion layers needs to be determined based on such an arrangement that the isolation characteristics between the wells and the diffusion layers become worst.
As has been described, degradation in the effective isolation width between the wells and the diffusion layers (degradation in the isolation characteristics) caused by impurity ion implantation for forming wells performed at a predetermined incident angle becomes a factor of hampering large-scale integration of a semiconductor device by reducing the isolation width between elements.
An object of the present invention is to provide a semiconductor device capable of suppressing degradation in the effective isolation width between a well and a diffusion layer caused by impurity ion implantation performed at a predetermined incident angle when forming the well, and a method of manufacturing the same.
According to a first aspect of the present invention, a semiconductor device includes an element isolation region and a well which is formed in an active region. The element isolation region is formed in a main surface of a semiconductor substrate and defines the active region. The well includes first and second impurity concentration peaks. The first impurity concentration peak is formed at a depth in the vicinity of a bottom of the element isolation region. The second impurity concentration peak is formed in a position deeper than the first impurity concentration peak. The first impurity concentration peak and the second impurity concentration peak are positionally shifted relative to each other in two directions different from each other in a plan view.
According to a second aspect of the present invention, a semiconductor device includes an element isolation region, a P well and an N well. The element isolation region is formed in a main surface of a semiconductor substrate and defines first and second active regions. The P well is formed in the first active region and shifted in a first direction relative to a depth direction of the semiconductor substrate. The N well is formed in the second active region and shifted in a second direction relative to the depth direction of the semiconductor substrate. The first and second directions are different from each other by 180 degrees in a plan view.
The unbalance of the isolation characteristics caused by the directional relationship between the wells and diffusion layers is reduced, and there can be no direction that the isolation characteristics are extremely degraded, which can contribute to large-scale integration of the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.